FM31T372/374/376/378-G
is reached internally, the address counter will wrap
to 0000h. Internally, the actual memory write occurs
after the 8th data bit is transferred. It will be complete
before the Acknowledge is sent. Therefore, if the
user desires to abort a write without altering the
memory contents, this should be done using a Start
or Stop condition prior to the 8th data bit. The figures
below illustrate a single- and multiple-writes to
memory.
Stop
Start
S
Address & Data
By Master
Slave Address
0
A
Address MSB
A
Address LSB
A
Data Byte
A
P
BByyFMFM313T13x7xxx
Acknowledge
Figure 12. Single Byte Memory Write
Start
Stop
P
Address & Data
By Master
S
Slave Address
0
A
Address MSB
A
Address LSB
A
Data Byte
A
Data Byte
A
By FM31xxx
By FM31T37x
Acknowledge
Figure 13. Multiple Byte Memory Write
transfers. After each byte the internal address counter
will be incremented.
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM31T37x uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to first
set the address to a specific value.
Each time the bus master acknowledges a byte,
this indicates that the FM31T37x should read
out the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM31T37x attempts to
read out additional data onto the bus. The four valid
methods follow.
Current Address & Sequential Read
As mentioned above the FM31T37x uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
1. The bus master issues a NACK in the 9th clock
cycle and a Stop in the 10th clock cycle. This is
illustrated in the diagrams below and is
preferred.
2. The bus master issues a NACK in the 9th clock
cycle and a Start in the 10th.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the
FM31T37x will begin shifting data out from the
current address on the next clock. The current address
is the value held in the internal address latch.
3. The bus master issues a Stop in the 9th clock
cycle.
4. The bus master issues a Start in the 9th clock
cycle.
If the internal address reaches the top of memory, it
will wrap around to 0000h on the next read cycle.
The figures below show the proper operation for
current address reads.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
Rev. 1.1
Apr. 2011
Page 18 of 26
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
