FM31T372/374/376/378-G
02h
Timekeeping – Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10 sec.2
10 sec.1
10 sec.0
Seconds.3
Seconds.2
Seconds.1
Seconds.0
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write.
01h
OSC/Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
CALS
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
/OSCEN
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the
oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1.
Battery-backed, read/write.
CALS
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from
the time-base. Calibration is explained on page 8. This bit is factory programmed. Nonvolatile, read/write.
These six bits control the calibration of the clock. These bits are factory programmed. Nonvolatile, read/write.
CAL.5-0
00h
Flags/Control
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
CF
Reserved
Reserved
Reserved
CAL
W
R
Reserved
CF
Reserved bits. Do not use. Should remain set to 0.
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This
indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new
century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user.
Battery-backed.
CAL
When set to 1, the CAL/PFO pin gives a 512 Hz square-wave output for clock audit. When CAL bit set to 0,
the clock operates normally, and the CAL/PFO pin is controlled by the power fail comparator. The CAL bit
must be cleared to enable temperature compensation. Temperature compensation is not applied to the 512Hz
frequency on the CAL/PFO pin. Battery-backed, read/write.
W
R
Write Time. Setting the W bit to 1 freezes the clock. The user can then write the timekeeping registers with
updated values. Resetting the W bit to 0 causes the contents of the time registers to be transferred to the
timekeeping counters and restarts the clock. Battery-backed, read/write.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.
Battery-backed, read/write.
Rev. 1.1
Apr. 2011
Page 15 of 26
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
