FM28V100_10 参数 Datasheet PDF下载

FM28V100 - 128Kx8 FRAM

Electrical Specifications

Absolute Maximum Ratings

Symbol

Description

V

DD

Power Supply Voltage with respect to V

SS

V

IN

Voltage on any signal pin with respect to V

SS

T

STG

T

LEAD

V

ESD

Storage Temperature

Lead Temperature (Soldering, 10 seconds)

Electrostatic Discharge Voltage

- Human Body Model

(AEC-Q100-002 Rev. E)

- Charged Device Model

(AEC-Q100-011 Rev. B)

- Machine Model

(AEC-Q100-003 Rev. E

)

Package Moisture Sensitivity Level

Ratings

-1.0V to +4.5V

-1.0V to +4.5V and

V

IN

< V

DD

+1V

-55°C to +125°C

260° C

2kV

1.25kV

200V

MSL-3

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating

only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this

specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions

(T

A

= -40° C to +85° C, V

DD

= 2.0V to 3.6V unless otherwise specified)

Symbol Parameter

Min

Typ

Max

Units Notes

V

DD

Power Supply

2.0

3.3

3.6

V

I

DD

V

DD

Supply Current

7

12

mA

1

I

SB

Standby Current – CMOS

90

150

2

µA

I

LI

Input Leakage Current

3

±1

µA

I

LO

Output Leakage Current

3

±1

µA

V

IH

Input High Voltage

0.7 V

DD

V

DD

+ 0.3

V

V

IL

Input Low Voltage

-0.3

0.3 V

DD

V

V

OH1

Output High Voltage (

I

OH

= -1 mA, V

DD

=2.7V)

2.4

V

V

OH2

Output High Voltage (

I

OH

= -100

µA)

V

DD

-0.2

V

V

OL1

Output Low Voltage (

I

OL

= 2 mA, V

DD

=2.7V)

0.4

V

V

OL2

Output Low Voltage (

I

OL

= 150

µA)

0.2

V

R

IN

Address Input Resistance (CE2)

4

For V

IN

= V

IH

(min)

40

KΩ

For V

IN

= V

IL

(max)

1

MΩ

Notes

1.

V

DD

= 3.6V, CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or V

DD

-0.2V), all DQ pins unloaded.

2.

V

DD

= 3.6V, /CE1 at V

DD

or CE2 at V

SS

, and all other pins at CMOS levels (0.2V or V

DD

-0.2V).

3.

V

IN

, V

OUT

between V

DD

and V

SS

.

4.

The input pull-up circuit is stronger (>40KΩ) when the input voltage is above V

IH

and weak (>1MΩ) when the input

voltage is below V

IL

.

Rev. 1.2

May 2010

Page 7 of 13