FM28V100 - 128Kx8 FRAM
Functional Truth Table
1
/CE1
CE2
H
X
X
L
H
↓
L
↑
L
H
L
H
H
↓
L
↑
L
H
L
H
H
↑
L
↓
/WE
X
X
H
H
H
H
L
L
↓
↓
X
X
A(16:3)
X
X
V
V
No Change
Change
V
V
V
No Change
X
X
A(2:0)
X
X
V
V
Change
V
V
V
V
V
X
X
Operation
Standby/Idle
Read
Page Mode Read
Random Read
/CE-Controlled Write
2
/WE-Controlled Write
2, 3
Page Mode Write
4
Starts Precharge
Notes:
1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care.
2) For write cycles, data-in is latched on the rising edge of /CE1 or /WE of the falling edge of CE2, whichever
comes first.
3) /WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then.
4) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.
Rev. 1.2
May 2010
Page 3 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
