FM28V100 - 128Kx8 FRAM
Overview
The FM28V100 is a bytewide F-RAM memory
logically organized as 131,072 x 8 and is accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page is triggered
by toggling a chip enable pin or simply by changing
the upper address A(16:3).
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when the device is activated with a chip enable.
In this case, the device begins the memory cycle as a
write. The FM28V100 will not drive the data bus
regardless of the state of /OE as long as /WE is low.
Input data must be valid when the device is
deselected with a chip enable. In a /WE-controlled
write, the memory cycle begins when the device is
activated with a chip enable. The /WE signal falls
some time later. Therefore, the memory cycle begins
as a read. The data bus will be driven if /OE is low,
however it will hi-Z once /WE is asserted low. The
/CE- and /WE-controlled write timing cases are
shown on page 12. In the
Write Cycle Timing 2
diagram, the data bus is shown as a hi-Z condition
while the chip is write-enabled and before the
required setup time. Although this is drawn to look
like a mid-level voltage, it is recommended that all
DQ pins comply with the minimum V
IH
/V
IL
operating
levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the deassertion of /WE, /CE1, or
CE2, whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE, /CE1, or CE2. Data setup
time indicates the interval during which data cannot
change prior to the end of the write access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FM28V100 provides the user fast access to any
data within a row element. Each row has eight
column locations (bytes). An access can start
anywhere within a row and other column locations
may be accessed without the need to toggle the CE
pins. For page mode reads, once the first data byte is
driven onto the bus, the column address inputs A(2:0)
may be changed to a new value. A new data byte is
then driven to the DQ pins. For page mode writes,
the first write pulse defines the first write access.
While the device is selected (both chip enables
asserted), a subsequent write pulse along with a new
column address provides a page mode write access.
Memory Operation
Users access 131,072 memory locations with 8 data
bits each through a parallel interface. The F-RAM
array is organized as 16,384 rows and each row has 8
column locations (bytes), which allows fast access in
page mode operation. Once an initial address has
been latched by the falling edge of /CE1 (while CE2
high) or the rising edge of CE2 (while /CE1 low),
subsequent column locations may be accessed
without the need to toggle a chip enable. When either
chip enable pin is deasserted, a precharge operation
begins. Writes occur immediately at the end of the
access with no delay. The /WE pin must be toggled
for each write operation.
Read Operation
A read operation begins on the falling edge of /CE1
(while CE2 high) or the rising edge of CE2 (while
/CE1 low). The /CE-initiated access causes the
address to be latched and starts a memory read cycle
if /WE is high. Data becomes available on the bus
after the access time has been satisfied. Once the
address has been latched and the access completed, a
new access to a random location (different row) may
begin while both chip enables are still active. The
minimum cycle time for random addresses is t
RC
.
Note that unlike SRAMs, the FM28V100’s /CE-
initiated access time is faster than the address cycle
time.
The FM28V100 will drive the data bus only when
/OE is asserted low and the memory access time has
been satisfied. If /OE is asserted prior to completion
of the memory access, the data bus will not be driven
until valid data is available. This feature minimizes
supply current in the system by eliminating transients
caused by invalid data being driven onto the bus.
When /OE is inactive, the data bus will remain hi-Z.
Write Operation
Writes occur in the FM28V100 in the same time
interval as reads. The FM28V100 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE1 (while
CE2 high) or the rising edge of CE2 (while /CE1
low).
Rev. 1.2
May 2010
Page 4 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
