FM25CL64B - 64Kb 3V SPI F-RAM
WRSR – Write Status Register
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25CL64B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25CL64B, /WP only prevents writing
to the Status Register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration (WREN not shown)
yellow). The WEL flag indicates the state of the
Status Register & Write Protection
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
The write protection features of the FM25CL64B are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /WP
pin. The Status Register is organized as follows.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
Table 2. Status Register
BP1
BP0 Protected Address Range
Bit
7
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
0
0
1
1
0
1
0
1
None
Name WPEN
WEL
1800h to 1FFFh (upper ¼)
1000h to 1FFFh (upper ½)
0000h to 1FFFh (all)
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit
0 (“Ready” in EEPROMs) is
unnecessary as the F-RAM writes in real-time and is
never busy. The WPEN, BP1 and BP0 control write
protection features. They are nonvolatile (shaded
Rev. 1.2
Feb. 2011
Page 6 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
