FM25CL64B - 64Kb 3V SPI F-RAM
WREN - Set Write Enable Latch
The FM25CL64B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Data Transfer
All data transfers to and from the FM25CL64B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
There are six commands called op-codes that can be
issued by the bus master to the FM25CL64B. They
are listed in the table below. These op-codes control
the functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
WRDI - Write Disable
Table 1. Op-code Commands
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Name
Description
Op-code
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
Set Write Enable Latch
Write Disable
WREN
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 1.2
Feb. 2011
Page 5 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
