FM24W256 - 256Kb Wide Voltage I2C F-RAM
Counter
Address
Latch
4,096 x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
A0-A2
Control Logic
Figure 1. Block Diagram
Pin Description
Pin Name
A0-A2
Type
Input
Pin Description
Device Select Address 0-2: These pins are used to select one of up to 8 devices of
the same type on the same two-wire bus. To select the device, the address value on
the three pins must match the corresponding bits contained in the slave address. The
address pins are pulled down internally.
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of
the part on the falling edge, and into the device on the rising edge. The SCL input
also incorporates a Schmitt trigger input for noise immunity.
Write Protect: When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
Supply Voltage: 2.7V to 5.5V
Ground
SDA
I/O
SCL
Input
WP
Input
VDD
VSS
Supply
Supply
Rev. 1.3
July 2011
Page 2 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
