FM24W256 - 256Kb Wide Voltage I2C F-RAM
AC Parameters
(T
A
= -40 C to + 85 C, V
DD
=2.7V to 5.5V unless otherwise specified)
Symbol Parameter
Min Max Min Max Min
f
SCL
SCL Clock Frequency
0
100
0
400
0
t
LOW
Clock Low Period
4.7
1.3
0.6
t
HIGH
Clock High Period
4.0
0.6
0.4
t
AA
SCL Low to SDA Data Out Valid
3
0.9
t
BUF
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
SP
Bus Free Before New Transmission
Start Condition Hold Time
Start Condition Setup for Repeated
Start
Data In Hold
Data In Setup
Input Rise Time
Input Fall Time
Stop Condition Setup
Data Output Hold
(from SCL @ V
IL
)
Noise Suppression Time Constant
on SCL, SDA
4.7
4.0
4.7
0
250
1000
300
4.0
0
50
0.6
0
50
1.3
0.6
0.6
0
100
300
300
0.25
0
50
0.5
0.25
0.25
0
100
300
100
Max
1000
0.55
Units
kHz
s
s
s
s
s
s
ns
ns
ns
ns
s
ns
ns
Notes
1
2
2
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1 The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from
DC to 1 MHz.
2 This parameter is periodically sampled and not 100% tested.
Capacitance
(T
A
= 25 C, f=1.0 MHz, V
DD
= 3V)
Symbol Parameter
Max
C
I/O
Input/Output Capacitance (SDA)
8
C
IN
Input Capacitance
6
Units
pF
pF
Notes
1
1
Notes
1 This parameter is periodically sampled and not 100% tested.
Power Cycle Timing
V
DD
V
DD
min.
t
VR
t
PU
t
PD
t
VF
SDA,SCL
Power Cycle Timing
(T
A
= -40 C to +85 C, V
DD
= 2.7V to 5.5V unless otherwise specified)
Symbol Parameter
Min
Max
t
PU
Power Up (V
DD
min) to First Access (Start condition)
10
-
t
PD
Last Access (Stop condition) to Power Down (V
DD
min)
0
-
t
VR
V
DD
Rise Time
30
-
t
VF
V
DD
Fall Time
100
-
Notes
1.
Slope measured at any point on V
DD
waveform.
Units
ms
s
s/V
s/V
Notes
1
1
Rev. 1.3
July 2011
Page 9 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
