FM24V02 - 256Kb I2C FRAM
Equivalent AC Test Load Circuit
AC Test Conditions
Input Pulse Levels
0.1 VDD to 0.9 VDD
10 ns
Input rise and fall times
Input and output timing levels
3.6V
0.5 VDD
1.8 Kohm
Output
Diagram Notes
All start and stop timing parameters apply to both read and write cycles.
Clock specifications are identical for read and write cycles. Write
timing parameters apply to slave address, word address, and write data
bits. Functional relationships are illustrated in the relevant datasheet
sections. These diagrams illustrate the timing parameters only.
100 pF
Read Bus Timing
tHIGH
tR
tSP
tF
tSP
tLOW
`
SCL
1/fSCL
tSU:SDA
tHD:DAT
tSU:DAT
tBUF
SDA
tDH
tAA
Stop Start
Acknowledge
Start
Write Bus Timing
tHD:DAT
SCL
tSU:DAT
tAA
tHD:STA
tSU:STO
SDA
Stop Start
Acknowledge
Start
Data Retention (TA = -40° C to +85° C)
Parameter
Data Retention
Min
10
Max
-
Units
Years
Notes
Rev. 0.1
Mar. 2009
Page 13 of 15
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