FM24V02 - 256Kb I2C FRAM
issues a start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a ‘1’. The
operation is now a current address read.
No
Acknowledge
Stop
Start
S
Address
By Master
Slave Address
1
A
Data Byte
Data
1
P
By FM24V05
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1
P
By FM24V05
Acknowledge
Data
Figure 8. Sequential Read
Start
No
Address
Acknowledge
Start
Address
By Master
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
S
Slave Address
1
A
Data Byte
Data
1 P
By FM24V05
Figure 9. Selective (Random) Read
Start
Start &
Enter HS-mode
No
Acknowledge
HS-mode command
Address
By Master
Stop &
Exit HS-mode
S
1
S
Slave Address
1
A
Data Byte
Data
1
P
0
0
0
0
1
X
X
X
By FM24V05
No
Acknowledge
Acknowledge
Figure 10. HS-mode Current Address Read
Start
Stop &
Exit HS-mode
Start &
Enter HS-mode
Address & Data
HS-mode command
By Master
S
1
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
Data Byte
A P
0
0
0
0
1
X
X
X
By FM24V05
No
Acknowledge
Figure 11. HS-mode Byte Write
Rev. 0.1
Mar. 2009
Page 7 of 15
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
