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FM24V02-GTR 参数 Datasheet PDF下载

FM24V02-GTR图片预览
型号: FM24V02-GTR
PDF下载: 下载PDF文件 查看货源
内容描述: 256Kb的3V串行F-RAM存储器 [256Kb Serial 3V F-RAM Memory]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 15 页 / 200 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号FM24V02-GTR的Datasheet PDF文件第7页浏览型号FM24V02-GTR的Datasheet PDF文件第8页浏览型号FM24V02-GTR的Datasheet PDF文件第9页浏览型号FM24V02-GTR的Datasheet PDF文件第10页浏览型号FM24V02-GTR的Datasheet PDF文件第12页浏览型号FM24V02-GTR的Datasheet PDF文件第13页浏览型号FM24V02-GTR的Datasheet PDF文件第14页浏览型号FM24V02-GTR的Datasheet PDF文件第15页  
FM24V02 - 256Kb I2C FRAM  
Electrical Specifications  
Absolute Maximum Ratings  
Symbol  
VDD  
Description  
Power Supply Voltage with respect to VSS  
Voltage on any pin with respect to VSS  
Ratings  
-1.0V to +4.5V  
VIN  
-1.0V to +4.5V  
and VIN < VDD+1.0V *  
TSTG  
TLEAD  
VESD  
Storage Temperature  
-55°C to +125°C  
300° C  
Lead Temperature (Soldering, 10 seconds)  
Electrostatic Discharge Voltage  
- Human Body Model (JEDEC Std JESD22-A114-B)  
- Charged Device Model (JEDEC Std JESD22-C101-A)  
- Machine Model (JEDEC Std JESD22-A115-A)  
Package Moisture Sensitivity Level  
TBD  
TBD  
TBD  
MSL-1  
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating  
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this  
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.0V to 3.6V unless otherwise specified)  
Symbol Parameter  
Min  
Typ  
Max  
Units  
Notes  
VDD  
IDD  
Main Power Supply  
2.0  
3.3  
3.6  
V
VDD Supply Current  
@ SCL = 100 kHz  
@ SCL = 1 MHz  
@ SCL = 3.4 MHz  
1
175  
400  
µA  
µA  
µA  
µA  
1000  
ISB  
Standby Current  
90  
5
150  
2
2
3
3
IZZ  
Sleep Mode Current  
Input Leakage Current  
8
µA  
ILI  
±1  
µA  
µA  
V
ILO  
Output Leakage Current  
±1  
VIL  
VIH  
VOL1  
VOL2  
RIN  
Input Low Voltage  
-0.3  
0.7 VDD  
0.3 VDD  
VDD + 0.3  
0.4  
Input High Voltage  
V
Output Low Voltage (IOL = 2 mA, VDD 2.7V)  
Output Low Voltage (IOL = 150 µA)  
Address Input Resistance (WP, A2-A0)  
For VIN = VIL (max)  
V
0.2  
V
50  
1
0.05 VDD  
5
4
KΩ  
MΩ  
V
For VIN = VIH (min)  
Input Hysteresis  
VHYS  
Notes  
1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.  
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.  
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.  
4. This parameter is characterized but not tested.  
5. The input pull-down circuit is stronger (50K) when the input voltage is below VIL and weak (1M) when the input voltage  
is above VIH.  
Rev. 0.1  
Mar. 2009  
Page 11 of 15