RA8835A
Version 1.0
Dot Matrix LCD Controller
CS
A0
RD
D6(flag)
0: Period of retrace lines
1: Period of display
0
0
0
Figure 7-7: Flowchart for Busy Flag Checking
• Precaution on the write timing to VRAM
The allowable writing duration is since “5 x 9 x tOSC” has elapsed (tOSC = 1/fOSC: a cycle of the oscillation
frequency) from the positive going edge of LP up to {(TCR) – (C/R) – 7} x 9 x tOSC
.
Currently employed D6 status flag reading method does not identify the timing when the read D6 =
Low took place. Thus, negative going edge of LP should be used as the interrupt signal when
implementing the writing in above timing. If you try to access the display memory in other timing than
the above, flickering of the display screen will result.
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