RA8835A
Version 1.0
Dot Matrix LCD Controller
7-4 Static RAM
The figure below shows the interface between an 8Kx8 static RAM and the RA8835A series. Note that
bus buffers are required if the bus is heavily loaded.
Note
VA0 to VA12
A0 to A12
HC138
A-C
VA13 toVA15
CS1
Y
2764-pin
Compatible
memory
VDD
RA8835
CE2
WRD
VWR
OE
WR
VD0 to VD7
I/O1 to I/O8
Figure 7-3: Static RAM Interface
Note: If the bus loading is too much, use a bus buffer.
7-5 Supply Current during Display Memory Access
The 24 address and data lines of the RA8835A series cycle at one-third of the oscillator frequency, fOSC
The charge and discharge current on these pins, IVOP, is given by the equation below. When IVOP
exceeds IOPR, it can be estimated by:
.
∝
IVOP
C V f
Where C is the capacitance of the display memory bus, V is the operating voltage, and f is the
operating frequency. If VOPR = 5.0V, f = 1.0 MHz, and the display memory bus capacitance is 1.0 pF
per line:
IVOP ≤ 120 mA / MHz x pF
To reduce current flow during display memory accesses, it is important to use low-power memory, and
to minimize both the number of devices and the parasitic capacitance.
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