RA8835A
Version 1.0
Dot Matrix LCD Controller
7-2-2 Internal Register Access
The SYSTEM SET and SLEEP IN commands can be used to perform input/output to the RA8835A
series independently of the system clock frequency. These are the only commands that can be
used while the RA8835A series is in sleep mode.
7-2-3 Display Memory Access
The RA8835A series supports a form of pipelined processing, in which the microprocessor
synchronizes its processing to the RA8835A series timing. When writing, the microprocessor first
issues the MWRITE command. It then repeatedly writes display data to the RA8835A series using
the system bus timing. This ensures that the microprocessor is not slowed down even if the display
memory access times are slower than the system bus access times. See Figure 7-1A.
tCYC
WR
Command write
Data write
Data write
Microprocessor
D0 to D7
VR/ W
VRW
VD0 to VD7
Figure 7-1A: Display Memory Write Cycle
When reading, the microprocessor first issues the MREAD command, which causes the RA8835A
series to load the first read data into its output buffer. The microprocessor then reads data from the
RA8835A series using the system bus timing. With each read, the RA8835A series reads the next
data item from the display memory ready for the next read access. See Figure 7-1B.
Figure 7-1B: Display Memory Read Cycle
Note: A possible problem with the display memory read cycle is that the system bus access time,
tACC, does not depend on the display memory access time, tACV. The microprocessor may
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