RA8806
Preliminary Version 1.0
Two Layers Character/Graphic LCD Controller
REG [D1h] PWM Duty Cycle Register (PDCR)
Bit
Description
Default
00h
Access
R/W
PWM Cycle Duty Selection Bit
00h Æ 1 / 256
01h Æ 2 / 256 High period
02h Æ 3 / 256 High period
7-0
:
:
FFh Æ 256 / 256 High period
REG [E0h] Pattern Data Register (PNTR)
Bit
Description
Default
00h
Access
R/W
Data Written to DDRAM(Display Data RAM)
The pattern that will be filled to active window in memory clear
function.
7-0
When REG[F0h] Bit-3 is ‘1’, the data in the REG[E0h] will be filled to
the whole active window.
REG [F0h] Font Control Register (FNCR)
Bit
Description
Default
0
Access
R/W
R
ISO8859 Mode
0 : Disable. The contents of ASCII block 1 ~ 4 are show as Table C-1~
Table C-4 of Appendix B.
1 : Enable. The ASCII block 1 ~ 4 indicate the ISO8859-1 ~ 4
standard and show as Table C-5 ~ Table C-8 of Appendix C.
7
Reserved
6-4
000
Memory Clear Function
Write Function
0 : No Action.
1 : Memory clear function active, fill the data of FNTR to Active
window.
3
0
R/W
When this bit is set to “1”, RA8806 will automatically read PNTR data,
and fill it to Active window (Range: [AWLR, AWTR] ~ [AWRR,
AWBR]), after clear completed, this bit will be cleaned to “0”.
ASCII Mode Enable
1 : All input data will be decoded as ASCII (00h ~ FFh)
0 : In text mode (REG[00h] Bit-3), the RA8806 will check the first
written byte data first. If less then 80h then it’s treated as ASCII
(Half-size). Or it’s treated as a full-size text(GB, BIG5 or User-
created font).
2
0
R/W
R/W
ASCII Blocks Select
0 0 : Map to ASCII block 1. (Table C-1 and Table C-5 of Appendix C.)
0 1 : Map to ASCII block 2. (Table C-2 and Table C-6 of Appendix C.)
1 0 : Map to ASCII block 3. (Table C-3 and Table C-7 of Appendix C.)
1 1 : Map to ASCII block 4. (Table C-4 and Table C-8 of Appendix C.)
1-0
00
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