RA8806
Preliminary Version 1.0
Two Layers Character/Graphic LCD Controller
REG [C3h] Touch Panel Segment/Common Low Byte Data Register (TPZR)
Bit
7-4
3-2
1-0
Description
Default
0000
00
Access
Reserved
R
R
R
Touch Panel Y Data Bit[1:0] (Common)
Touch Panel X Data Bit[1:0] (Segment)
00
REG [C4h] Touch Panel Control Register 2 (TPCR2)
Bit
7
Description
Default
0
Access
R/W
R
TP Manual Mode Enable
1 : Using the manual mode.
0 : Auto mode.
Reserved
6-2
00h
Mode selection for TP Manual Mode
00 : IDLE mode: ADC idles.
01 : Wait for TP event, touch panel event could cause the interrupt or
be read from REG[0Fh] B3.
10 : Latch X data, in the phase, X Data can be latched in REG[C1h]
and REG[C3h].
1-0
00
R/W
11 : Latch Y data, in the phase, Y Data can be latched in REG[C2h]
and REG[C3h].
REG [D0h] PWM Control Register (PCR)
Bit
7
Description
Default
0
Access
R/W
PWM enable
1 : Enable
0 : Disable, PWM_OUT level depends on the REG[D0h] Bit-6.
PWM Disable Level
0 : PWM_OUT is Normal L when PWM disable or Sleep mode.
1 : PWM_OUT is Normal H when PWM disable or Sleep mode.
Reserved
6
0
R/W
R
5-4
00
PWM Clock Source Divide Ratio
0000 b Æ CLK / 1
0001 b Æ CLK / 2
0010 b Æ CLK / 4
0011 b Æ CLK / 8
:
:
3-0
0000
R/W
1111 b Æ CLK / 32768
The “CLK” means system clock. For example, CLK is 8MHz:
0000 b Î PWM clock source = 8MHz,
0001 b Î PWM clock source = 4MHz,
:
:
1111 b Î PWM clock source = 256Hz.
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