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QT60326 参数 Datasheet PDF下载

QT60326图片预览
型号: QT60326
PDF下载: 下载PDF文件 查看货源
内容描述: 32和48个重点QMATRIX集成电路 [32 & 48 KEY QMATRIX ICs]
分类和应用:
文件页数/大小: 32 页 / 881 K
品牌: QUANTUM [ QUANTUM RESEARCH GROUP ]
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If the host desires to send a byte to the QT it should behave as  
follows:  
3 Serial Communications  
These devices can use either SPI or UART communications  
modes; it cannot use both at the same time. The part defaults to  
SPI mode unless it receives a byte over the UART interface. If a  
UART byte is received at any time, the UART interface is  
enabled and the SPI interface is totally disabled until after the  
next device reset.  
1. If DRDY is low, wait  
2. If DRDY is high: send a command to QT  
3. Wait 20µs (time S5 in Figure 3-3: DRDY is guaranteed to  
go low before this 20µs expires)  
4. Wait until DRDY is high (it may already be high again)  
5. Send next command or a null byte 0x00 to QT  
The host device always initiates communications sequences;  
the QT is incapable of chattering data back to the host. This is  
intentional for FMEA purposes so that the host always has total  
control over the communications with the QT60xx6. In SPI  
mode the device is a slave, so that even return data following a  
command is controlled by the host. In UART mode, the device  
will still only respond back to the host after a command, but the  
responses are not controlled by the host.  
It takes up to 1ms for DRDY to go high again after a command,  
except for a few commands listed in Section 4:  
0x01 (Setups load):  
0x0E (Get eeprom CRC):  
0x16 (Sleep):  
<20ms  
<20ms  
<5ms  
Other DRDY specs:  
Min time DRDY is low:  
1µs  
A command from the host always ends in a response of some  
kind from the QT. Some transmission types from the host or the  
QT employ a CRC check byte to provide for robust  
communications.  
Min time DRDY is low after reset:  
1ms  
3.2 SPI Communications  
SPI mode is selected by default after reset. There is no other  
configuration required to make the device operate in SPI mode.  
If a UART byte occurs before or even after SPI transmissions  
have taken place, the device will switch to UART mode and  
remain in that mode until the device is reset.  
A DRDY line is provided that handshakes transmissions.  
Generally this is needed by the host from the QT to ensure that  
transmissions are not sent when the QT is busy or has not yet  
processed a prior command. In UART mode this line is  
bi-directional, and the QT can use it to suspend transmissions  
back to the host if the host is busy.  
Initiating or Resetting Communications: After a reset, or,  
should communications be lost due to noise or out-of-sequence  
reception, the host should send a 0x0f (return last command)  
command repeatedly until the compliment of 0x0f, i.e. 0xf0, is  
received back. Then, the host can resume normal run mode  
communications from a clean start.  
Figure 3-1 Basic SPI Connections  
Host MCU  
QT60xx6  
Poll rate: The typical poll rate in normal ‘run’ operation should  
be no faster than once per 10ms; even 50ms is more than fast  
enough to extract status data using the 0x06 command (report  
first key: see page 15) in most situations. Streaming commands  
like the 0x0d command (dump setups: see page 15) or  
multi-byte response commands like 0x07 or 0x08 can and  
should pace at the maximum possible rate.  
P_IN  
P_OUT  
SCK  
MISO  
MOSI  
DRDY  
SS  
SCK  
MISO  
MOSI  
Run Poll Sequence: In normal run mode the host should limit  
traffic with a minimalist control structure (see also Section 4.23).  
The host should just send a 0x06 command until something  
requires a deeper state inspection. If there is more than one key  
in detect, the host should use 0x07 to find which additional keys  
are in detect. If there is an error, the host should ascertain the  
error type based on commands 0x0b and 0x0c and take  
appropriate action. Issuing a 0x07 command all the time is  
wasteful of bandwidth, requires more host processor time, and  
actually conveys less information (no error flags are sent via a  
0x07 command).  
Figure 3-2 Filtered SPI Connections  
Host MCU  
QT60xx6 Circuit  
X drives  
P_IN  
P_OUT1  
SCK  
DRDY  
Xn  
Yn  
Ra  
Ra  
Ra  
Ra  
(1 of 8  
Ca  
shown)  
SS  
Ca  
Ca  
SCK  
MISO  
MISO  
MOSI  
3.1 DRDY Pin  
Ca  
Y Lines  
(1 of 6  
DRDY is an open-drain output (in SPI mode) or bidirectional pin  
(in UART mode) with an internal 20K ~ 50K pull-up resistor.  
MOSI  
Ra  
1K  
shown)  
Ca  
Serial communications pacing is controlled by this pin. In either  
UART or SPI mode, the host is permitted to send data only  
when DRDY is high. In UART mode, the device additionally will  
hold up responses to the host if DRDY is being held low by the  
host. After a byte is received DRDY will always go low even if  
only for a few microseconds; during this period the host should  
not send data. Therefore, after each byte transmission the host  
should first check that DRDY is high again.  
P_OUT2  
RESET  
1nF  
Recommended Values of Ra & Ca  
SPI Clock Rate  
Ra  
Ca  
4MHz  
680  
33pF  
270pF  
470pF  
1nF  
400kHz  
1,000  
2,200  
2,200  
100kHz  
50kHz  
lQ  
11  
QT60486-AS R8.01/0105