Figure 2.7 Wiring Diagram
See Table 2.2 for further connection information.
VDD
+3 to +5V
Vunreg
VREG
Note 1
+
+
100nF
4.7uF
4.7uF
RX7
1K
RX6
1K
1K
DRDY
SS
RX5
1K
RX4
1K
MOSI
MISO
SCLK
RX3
1K
RX2
RX1
1K
RX0
1K
SCOPE SYNC
LINE SYNC
QT60248
QT60168
RY0
RY1
RY2
1K
1K
1K
CS0
4.7nF
4.7nF
4.7nF
CS1
Note 2
Note 2
CS2
Note 1: Wire 100nF bypass cap
very close to pins 3, 4, 5, 6
RS2
RS1
RS0
10K
100
VDD
470K 470K 470K
Note 2: Leave Y2A, Y2B unconnected
for QT60168
lQ
9
QT60248-AS R4.02/0405