欢迎访问ic37.com |
会员登录 免费注册
发布采购

QT60168 参数 Datasheet PDF下载

QT60168图片预览
型号: QT60168
PDF下载: 下载PDF文件 查看货源
内容描述: 16日, 24个重点QMATRIX集成电路 [16, 24 KEY QMATRIX ICs]
分类和应用:
文件页数/大小: 28 页 / 867 K
品牌: QUANTUM [ QUANTUM RESEARCH GROUP ]
 浏览型号QT60168的Datasheet PDF文件第6页浏览型号QT60168的Datasheet PDF文件第7页浏览型号QT60168的Datasheet PDF文件第8页浏览型号QT60168的Datasheet PDF文件第9页浏览型号QT60168的Datasheet PDF文件第11页浏览型号QT60168的Datasheet PDF文件第12页浏览型号QT60168的Datasheet PDF文件第13页浏览型号QT60168的Datasheet PDF文件第14页  
The time it takes for DRDY to go high again after a command  
depends on the command. Following is a list of commands and  
the time required to process them and then raise DRDY:  
3 Serial Communications  
These devices use SPI communications, in slave mode.  
The host device always initiates communications sequences;  
the QT is incapable of chattering data back to the host. This is  
intentional for FMEA purposes so that the host always has total  
control over the communications with the QT60xx8. In SPI  
mode the device is a slave, so that even return data following a  
command is controlled by the host.  
0x0E Eeprom CRC  
0x01 Load Setups  
All other commands:  
[ 25ms  
[ 25ms  
[ 2ms between bytes;  
[ 40µs after CRC byte is sent  
Other DRDY specs:  
Min time DRDY is low: 1µs  
Min time DRDY is low  
A command from the host always ends in a response of some  
kind from the QT. Some transmission types from the host or the  
QT employ a CRC check byte to provide for robust  
communications.  
after reset:  
1ms  
3.2 SPI Communications  
A DRDY line is provided that handshakes transmissions.  
Generally this is needed by the host from the QT to ensure that  
transmissions are not sent when the QT is busy or has not yet  
processed a prior command.  
SPI communications operates in slave mode only, and obeys  
DRDY control signaling. The clocking is as follows:  
Clock idle:  
High  
Clock shift out edge:  
Clock data in edge:  
Max clock rate:  
Falling  
Rising  
1.5MHz  
Initiating or Resetting Communications: After a reset, or,  
should communications be lost due to noise or out-of-sequence  
reception, the host should send a 0x0f (return last command)  
command repeatedly until the compliment of 0x0f, i.e. 0xf0, is  
received back. Then, the host can resume normal run mode  
communications from a clean start.  
SPI mode requires 5 signals to operate:  
MOSI - Master out / Slave in data pin; used as an input for  
data from the host (master). This pin should be connected  
to the MOSI (DO) pin of the host device.  
Poll rate: The typical poll rate in normal ‘run’ operation should  
be no faster than once per 10ms; 25ms is more than fast  
enough to extract status data using the 0x06 command (report  
first key: see page 13) in most situations. Streaming multi-byte  
response commands like the 0x0d command (dump setups: see  
page 13) or multi-byte response commands like 0x07 can and  
should pace at the maximum possible rate.  
MISO - Master in / Slave out data pin; used as an output for  
data to the host. This pin should be connected to the MISO  
Figure 3-1 Basic SPI Connections  
Run Poll Sequence: In normal run mode the host should limit  
traffic with a minimalist control structure (see also Section 4.18).  
The host should just send a 0x06 command until something  
requires a deeper state inspection. If there is more than one key  
in detect, the host should use 0x07 to find which additional keys  
are in detect. If there is an error, the host should ascertain the  
error type based on commands 0x0b and 0x0c and take  
appropriate action. Issuing a 0x07 command all the time is  
wasteful of bandwidth, requires more host processor time, and  
actually conveys less information (no error flags are sent via a  
0x07 command).  
Host MCU  
QT60xx8  
P_IN  
P_OUT  
SCK  
MISO  
MOSI  
DRDY  
SS  
SCK  
MISO  
MOSI  
Figure 3-2 Filtered SPI Connections  
3.1 DRDY Pin  
DRDY is an open-drain output with an internal 20K ~ 50K pullup  
resistor.  
Host MCU  
QT60xx8 Circuit  
X drives  
P_IN  
P_OUT1  
SCK  
DRDY  
Ra  
Ra  
Ra  
Ra  
Serial communications pacing is controlled by this pin. The host  
is permitted to send data only when DRDY is high. After a byte  
is received DRDY will always go low even if only for a few  
microseconds; during this period the host should not send data.  
Therefore, after each byte transmission the host should first  
check that DRDY is high again.  
(1 of 8  
Ca  
Ca  
1K  
1K  
Xn  
Yn  
shown)  
SS  
Ca  
Ca  
SCK  
MISO  
MISO  
MOSI  
Y Lines  
(1 of 3  
shown)  
If the host desires to send a byte to the QT it should behave as  
follows:  
MOSI  
Ra  
1K  
Ca  
1. If DRDY is low, wait  
P_OUT2  
RESET  
2. If DRDY is high: send a command to QT  
3. Wait at least 40µs (time S5 in Figure 3-3: DRDY is  
guaranteed to go low before this 40µs expires)  
4. Wait until DRDY is high (it may already be high again)  
5. Send next command or a null byte 0x00 to QT  
1nF  
Recommended Values of Ra & Ca  
SPI Clock Rate  
Ra  
Ca  
1.5MHz  
680  
100pF  
270pF  
470pF  
1nF  
400kHz  
1,000  
2,200  
2,200  
100kHz  
50kHz  
lQ  
10  
QT60248-AS R4.02/0405