The CAL_UP pin should be used to calibrate the signal when
the electrode is at its maximum useable level of Cx, for
example with a level probe when the fluid is at the top.
Figure 4-1 Calibration Process
User sets CAL_DN
high
User sets CAL_UP
high
It does not matter whether CAL_DN or CAL_UP are applied
first. After calibration is complete, either CAL_DN or CAL_UP
can be asserted again to obtain a fresh calibration for the
corresponding end point, without affecting the other end
point.
2.5ms Delay
2.5ms Delay
CAL_DN forced high
by QT301
CAL_UP forced high
by QT301
4.2 Calibration Process
The CAL pins are inputs used to trigger a CAL process on
the upper (max Cx) or lower (min Cx) capacitance endpoints.
These pins must be pulled low via a pulldown resistor on
each, to prevent damage.
Calibration starts
Calibration starts
User floats CAL_DN
User floats CAL_UP
To calibrate either endpoint, assert either CAL pin high using
an open-source output from a mosfet or microcontroller, or, a
collector from a PNP transistor whose emitter is connected to
Vdd. Hold this level high for 2.5ms minimum (preferably, 3ms
to be safe). Then release the pin to try to float down.
NO
NO
QT301 Cal done?
QT301 Cal done?
The QT301 will continue to hold the pin high starting at the
2.5ms point. There should be no contention problem with an
external voltage plus the QT301 both holding this pin high.
YES
YES
QT301 floats
CAL_DN pin again
QT301 floats
CAL_UP pin again
When the QT301 is done calibrating, it will release the CAL
pin in question to float low. A host controller can use this
feature to check when the calibration process has completed.
If the power supply is shared with another electronic system,
make sure the supply is free of spikes, sags, and surges.
The supply is best locally regulated using a conventional
78L05 type regulator, or almost any 3-terminal LDO device
from 3V to 5V.
Calibration takes 15 acquisition burst samples to complete.
The new calibration data is stored in internal EEPROM when
the host releases the CAL pin to float low again; the chip also
begins to operate normally again at this time.
Figure 4-1 shows the control flows for calibration.
For proper operation, a 0.1µF or greater bypass capacitor
must be used between VDD and VSS; the bypass cap should
be placed very close to the device pins. The PCB should if
possible include a copper pour under and around the IC, but
not extensively under the SNS pins or lines.
The capacitive signal on the electrode should be as stable
and noise-free as possible during the CAL intervals to ensure
accurate calibration points.
During a CAL cycle, the PWM output functions normally
using the last known good calibration data and signal value.
The PWM output will change again only when the CAL
process is complete.
5.3 ESD Protection
In cases where the electrode is placed behind a dielectric
panel the IC will be protected from direct static discharge.
However, even with a panel transients can still flow into the
electrodes via induction, or in extreme cases via dielectric
breakdown. Porous materials may allow a spark to tunnel
right through the material. Testing is required to reveal any
problems.
Note: The CAL pins should never be driven low. Driving
either of the CAL pins low will short circuit the chip.
5 - CIRCUIT GUIDELINES
5.1 Sample Capacitor
The device has diode protection on its SNS pins that absorb
most induced discharges (up to 20mA), and protect the
device. The usefulness of the internal clamping will depend
on the dielectric properties, panel thickness, and rise time of
the ESD transients. In extreme cases, ESD dissipation can
be aided further by adding a resistor in series with the
electrode.
The charge sampler capacitor (Cs) can be virtually any
plastic film or low to medium-K ceramic capacitor. The
acceptable Cs range is from 1nF to 500nF depending on the
sensitivity required; larger values of Cs demand higher
stability to ensure reliable sensing. Acceptable capacitor
types include plastic film (especially PPS film) and NP0/C0G
ceramic. X7R ceramic can also be used but this type is less
stable over temperature.
The charge pulse can be a minimum of 1µs and therefore the
circuit can tolerate values of series-R up to 18k in cases
where electrode Cx load is below 10pF. Extra diode
protection may be used at the electrodes but this often leads
to additional RFI problems as the diodes will rectify RF
signals into DC; this will disturb the sensing signals.
Series-R’s should be low enough to permit at least six RC
time-constants (i.e. a net RC timeconstant of 1/6 µs) to occur
during the charge pulse, where R is the added series-R and
5.2 Power supply, PCB Layout
The QT301 makes use of the power supply as a reference
voltage. The acquired signal will shift slightly with changes in
VDD; fluctuations in VDD often happen when additional loads
are switched on or off such as LEDs etc.
Care should be taken when designing the power supply, as
any change in VDD will affect the PWM level.
LQ
5
QT301 R1.06 12/03
QUANTUM [ QUANTUM RESEARCH GROUP ]
