1 - Overview
The QT301 is a digital burst mode charge-transfer (QT)
capacitance-to-analog converter (CAC). It has a PWM output
designed for applications such as fluid level sensing and
distance gauging; the PWM signal is eight bits in resolution.
The IC features two calibration inputs for end-to-end span
calibration. The output depends on load (Cx) and sampling
capacitor (Cs) values.
Pin
1
2
3
4
5
6
7
8
Table 1-1 Pin Description
Name
SYNC
CAL_DN
SNS1
VSS
SNS2
PWM
CAL_UP
VDD
Function
Sync Input
Lower Calibration input
Sense 1 line (to electrode)
Negative supply (ground)
Sense 2 line
PWM output
Upper Calibration input
Positive supply
1.1 Basic Operation
The QT301 has internal EEPROM to store the two calibration
points. The sensor acquires the signal from the electrode and
calculates the PWM result using the two calibration points.
The sensor can be calibrated via the two calibration inputs
(see Section 4). The signal can be acquired either
continuously or it can be synchronized on an external signal.
The response time of the PWM depends largely on the
acquisition burst spacing.
Figure 1-1 Basic Circuit Diagram
3 to 5.5V
0.1uF
2 - Signal Acquisition
The QT301 has a power-up delay of 300ms. During this
interval it does not acquire signals or generate a PWM result;
it also ignores calibration inputs. This delay helps to prevent
false calibrations due to signal noise on Vdd during
startup.
Figure 2-1 shows the basic QT301 acquisition timing
parameters. Tbd is the burst duration, Tbs is the
burst spacing from the start of one burst to the start
of the next burst; when there is no Sync signal Tbs =
Tbd+2.5ms.
R1
8
1
7
2
6
VDD
SYNC
CAL_UP
CAL_DN
Electrode
SNS1
SNS2
Rs
2.1 Burst Properties
The QT301 employs bursts of charge-transfer cycles
to acquire its signal. Burst mode dramatically reduces
RF emissions and lowers susceptibility to EMI.
The acquisition burst operates in a band between
230kHz and 310kHz. The burst is spread-spectrum
modulated within this band to suppress interference
from external noise sources.
Upper Cal
3
5
Cs
Lower Cal
Cx
PWM Out
PWM
VSS
R3
R2
4
1.2 Basic Circuit
Figure 1-1 shows a basic circuit diagram for the QT301. The
pin layout of the QT301 is as explained in Table 1-1. In this
particular circuit, C1 should be 100nF and R1, R2 and R3
should all be 10K.
R1 is only required if the synchronization feature is not used
and can be connected to either VDD or VSS.
Cs should be between 1nF and 500nF depending on the
sensitivity required. Use either NPO or PPS capacitors for
best results.
Rs is calculated with the following formula:
The QT switches and charge measurement hardware
functions are all internal to the QT301. A 16-bit
single-slope switched capacitor, analog to digital
converter (ADC), includes both the required QT
charge and transfer switches in a configuration that
provides direct ADC conversion. The ADC is designed to
dynamically optimize the QT burst length according to the
rate of charge buildup on Cs, which in turn depends on the
values of Cs, Cx, and VDD. VDD is used as the charge
reference voltage.
Figure 2-1 Acquisition Burst: No Sync Pulse
Rs
<
where Cx is expressed in pF.
166%10
3
Cx
Tbd
Tbs
LQ
2
QT301 R1.06 12/03
QUANTUM [ QUANTUM RESEARCH GROUP ]
