The 2.5ms is the minimum gap between bursts is to
allow Cs to properly discharge; Sync is not possible
during this interval nor is it possible to re-sync during a
burst.
PWM, 0..255
% Error
Figure 2-6 PWM vs Cx, Over Range 100pF...110pF
300
250
200
150
100
50
3%
2%
2%
1%
1%
0%
3 PWM Output
The PWM output is a 100KHz 7% square wave. It
can be filtered using a simple RC circuit, or fed directly
into a timer circuit that can measure its duty cycle with
sufficient resolution. If an RC is used, the resistor
should be at least 10K ohms to reduce pin loading
errors.
The PWM duty cycle is defined as follows:
0
100
101
102
103
104
105
106
107
108
109
110
TPWM_high
Cx, pF
DPWM
=
TPWM_Period
If an RC circuit is used, it is often best to put a voltage
follower circuit on the output of the filter to buffer the output
voltage (Figure 2-7).
2.4 Sync Input
Bursts can be synchronized to external noise sources such
as powerline fields to suppress their interferening effects. A
typical sync circuit is shown in Figure 2-7. By synchronizing
with a noise source, the noise itself becomes highly
correlated with the acquired data, and AC alias components
effectively disappear from the signal. Synchronization works
best on low frequency, highly repeatable signals, such as
mains frequency (50/60 Hz) sources.
Note that the PWM output is not 100% linear with changes in
Cx capacitance from end to end. The transfer function for the
QT301 vs Cx is described in Section 2.3.
During CAL, the PWM output value is locked in place with
the value just prior to when the CAL process was triggered.
Only after CAL is complete is the PWM updated with the new
results.
Figure 2-2 shows the effect of sync pulses on the burst rate.
A sync signal triggers a burst on the rising edge.
4 Calibration
There is a Sync timeout of 100ms as shown in Figure 2-3. If
Sync pulses cease for >100ms, the Sync signal will be
treated as being lost and the device will start to acquire at its
own default rate again. When using the Sync feature it is
important that the Sync pulses are spaced less than 100ms
apart.
The QT301 should be calibrated end to end to have an
effective, properly scaled PWM output. The calibration is
done on a ‘learn by example’ basis. Each end is calibrated
separately while the appropriate end-point signal level is
applied. After the Cal process, the PWM signal will scale
itself to reflect these endpoints with the best resolution
possible.
Figure 2-2 shows the acquisition burst in relation to Sync
pulses. If no rising edge is detected for 100ms, the QT301
will revert to the default timing shown in Figure 2-1. Figure
2-4 shows the sudden start of a train of Sync pulses and the
effect on the acquisition bursts.
4.1 Calibration Pins
The CAL_DN pin should be used to calibrate the signal when
the electrode is at its lowest level of Cx, for example with a
level probe when the fluid is at a minimum.
Should the sync signal overclock the acquisition bursts
(Figure 2-5), the device will trigger on the next rising edge
after a delay of Tbd+2.5ms.
Figure 2-7 Line Sync and PWM Output Filter
+3 to 5.5V
0.1uf
IN4148
8
VDD
1M
1
Line
Frequency
SYNC
Electrode
20pF
Rs
7
2
6
3
5
CAL_UP
CAL_DN
PWM
Upper Cx Cal
SNS1
SNS2
Cs
Lower Cx Cal
Cx
100K
Analog
Output
VSS
0.1uF
10K
10K
4
LQ
4
QT301 R1.06 12/03
QUANTUM [ QUANTUM RESEARCH GROUP ]
