QN8006B/8006LB
Figure 8: Timing for QN8006 as I2S Slave and Receiver
Table 14: Timing for QN8006 as I2S Slave and Receiver
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
T
tLC
tHC
ts
I2S clock frequency
Clock low time
100
10
10
10
5
ns
ns
ns
ns
ns
Clock high time
WS and SD setup time
WS and SD hold time
Clock rise-time
th
tRC
tFC
5
5
ns
ns
Clock fall-time
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
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