QN8006B/8006LB
3.1 I2S Interface Timing
Note: The terms 'transmitter' and 'receiver' as described below are from the QN8006's point of view.
Either the QN8006 or the external device can act as the system master by providing the necessary clock signals. The slave
will usually derive its internal clock signal from an external clock input. This means, taking into account the propagation delay
between the master clock and the data and/or word-select signals, that the total delay is simply the sum of:
•
•
The delay between the external (master) clock and slave’s internal clock;
The delay between the internal clock and the data and/or word-select signals.
For data and word-select inputs, the external to internal clock delay is of no consequence because it only lengthens the
effective set-up time (see Figure 6). The major part of the time margin is to accommodate the difference between the
propagation delay of the transmitter, and the time required to set up the receiver. All timing requirements are specified
relative to the clock period or to the minimum allowed clock period of a device. This means that higher data rates can be
used in the future.
Figure 6: Timing for QN8006 as I2S Slave and Transmitter
Table 12: Timing for QN8006 as I2S Slave and Transmitter
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
T
tLC
tHC
ts
I2S clock period
Clock low time
Clock high time
WS setup time
WS hold time
SD delay time
Clock rise-time
Clock fall-time
100
10
10
10
5
ns
ns
ns
ns
ns
th
tdtr
tRC
tFC
10
5
ns
ns
ns
5
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
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