Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
This chapter describes the IDD Specifications and Conditions.
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Table 20 “IDD Measurement Conditions” on Page 30
Table 21 “Definitions for IDD” on Page 31
Table 22 “IDD Specification for HYS72T[64/128/256]xxxHR–3–A” on Page 32
Table 23 “IDD Specification for HYS2T[64/128/256]xxxHR–3S–A” on Page 33
Table 24 “IDD Specification for HYS72T[64/128/256]xxxHR–3.7–A” on Page 34
Table 25 “IDD Specification for HYS72T[64/128/256]xxxHR–5–A” on Page 35
TABLE 20
IDD Measurement Conditions
Parameter
Symbol Note1)2)3)4)5)6)7)8)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is
HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS
RAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid
=
t
commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
;
t
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
;
t
RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
Rev. 1.31, 2006-11
30
03292006-21GC-MK06
QIMONDA [ QIMONDA AG ]
