Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note1)2)3)4)5)6)7)8)
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Distributed Refresh Current
IDD5D
IDD6
IDD7
t
CK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are
guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4.
Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 21
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh)
7) All current measurements includes Register and PLL current consumption
8) For details and notes see the relevant Qimonda component data sheet
TABLE 21
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.31, 2006-11
31
03292006-21GC-MK06
QIMONDA [ QIMONDA AG ]
