Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–600
2
+600
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
8)22)
9)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
275
—
—
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DH1(base)
DQ and DM input hold time (single ended data
strobe)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–500
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+500
—
DQS input low (high) pulse width (write cycle) tDQSL,H
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
350
Write command to 1st DQS latching transition tDQSS
– 0.25
150
+ 0.25
—
tCK
11)
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
–25
0.2
—
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
350
—
ps
ps
ps
tCK
ns
—
ps
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
450
Rev. 1.31, 2006-11
26
03292006-21GC-MK06
QIMONDA [ QIMONDA AG ]
