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HYS72T256220HR-3S-A 参数 Datasheet PDF下载

HYS72T256220HR-3S-A图片预览
型号: HYS72T256220HR-3S-A
PDF下载: 下载PDF文件 查看货源
内容描述: 240引脚注册DDR2 SDRAM模组 [240-Pin Registered DDR2 SDRAM Modules]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 74 页 / 4051 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A  
Registered DDR2 SDRAM Modules  
3.3  
Timing Characteristics  
This chapter describes the AC characteristics tables.  
3.3.1  
Speed Grades Definitions  
Speed Grade Definitions for: DDR2–667 (Table 12), DDR2–533C (Table 13) and DDR2–400B (Table 14)  
TABLE 12  
Speed Grade Definition Speed Bins for DDR2–667  
Speed Grade  
DDR2–667C  
DDR2–667D  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
–3  
–3S  
4–4–4  
5–5–5  
tCK  
Parameter  
Symbol  
Min.  
Max.  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
5
8
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
3
8
3.75  
3
8
tCK  
3
8
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
45  
57  
12  
12  
70000  
45  
60  
15  
15  
70000  
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0) .  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
TABLE 13  
Speed Grade Definition Speed Bins for DDR2–533C  
Speed Grade  
DDR2–533C  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
–3.7  
4–4–4  
tCK  
Parameter  
Symbol  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
tCK  
tCK  
tRAS  
tRC  
5
8
ns  
ns  
ns  
ns  
ns  
3.75  
3.75  
45  
8
8
Row Active Time  
Row Cycle Time  
70000  
60  
Rev. 1.31, 2006-11  
17  
03292006-21GC-MK06  
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