Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.31, 2006-11
13
03292006-21GC-MK06
QIMONDA [ QIMONDA AG ]
