Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.2
Component AC Timing Parameters
Speed Grade Definitions for: DDR2–667 (Table 15), DDR2–533C (Table 16) and DDR2–400B (Table 17)
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–450
–400
0.48
0.48
3000
100
+450
+400
0.52
0.52
8000
—
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
tCK.AVG
tCK.AVG
ps
12)13)14)
13)14)15)
DQ and DM input setup time
DQ and DM input hold time
ps
175
—
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
9)16)
9)16)
17)
tAC.MAX
tAC.MAX
tAC.MAX
240
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min(tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
340
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL–1
nCK
tCK.AVG
21)
DQS latching rising transition to associated clock tDQSS
– 0.25
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
—
—
—
0.6
—
—
—
1.1
0.6
—
—
—
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
21)
21)
tDSH
0.2
tWPST
tWPRE
tIS.BASE
tIH.BASE
tRPRE
tRPST
tCCD
0.4
Write preamble
0.35
200
275
0.9
22)23)
23)24)
25)26)
25)27)
Address and control input setup time
Address and control input hold time
Read preamble
ps
tCK.AVG
tCK.AVG
nCK
Read postamble
0.4
CAS to CAS command delay
Write recovery time
2
1)
tWR
15
ns
28)29)
1)30)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
Internal write to read command delay
tWTR
ns
Rev. 1.31, 2006-11
19
03292006-21GC-MK06
QIMONDA [ QIMONDA AG ]
