HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Overview
1
Overview
1.1
Features
•
184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Server main memory
applications
•
•
One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
and +2.6V (±0.1V) ppower supply for DDR400
•
•
•
•
•
•
•
•
•
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Table 1
Performance
Product Type Speed Code
Module Speed Grade
Component Module
–5
–6
Unit
—
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
—
Max. Clock Frequency
@ CL = 3
@ CL = 2.5
@ CL = 2
fCK3
MHz
MHz
MHz
fCK2.5
fCK2
166
166
133
133
1.2
Description
The HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C,
HYS64D[16/32/64][300/301/320][G/H]U–6–C and HYS72D[32/64][300/301/320][G/H]U–6–C are industry
standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 16M ×64, 32M ×64 and 64M ×64
for non-parity and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is designed
with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the
printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer
Internet Data Sheet
3
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
QIMONDA [ QIMONDA AG ]
