HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 7
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
SDRAMs columns bits
Ranks
128MB
256MB
256MB
512MB
512MB
16M ×64
32M ×64
32M ×72
64M ×64
64M ×72
1
1
1
2
2
16M ×16
32M ×8
32M ×8
32M ×8
32M ×8
4
13/2/9
8K
8K
8K
8K
8K
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
8
13/2/10
13/2/10
13/2/10
13/2/10
9
16
18
Internet Data Sheet
9
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4