Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
TABLE 6
Address Format
Density
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period Interval
256 MB
512 MB
512 MB
1 GB
32M ×64
64M ×64
64M ×72
128M ×64
128M ×72
1
1
1
2
2
32M ×16
64M ×8
64M ×8
64M ×8
64M ×8
4
13/2/9
8K
8K
8K
8K
8K
64 ms
64 ms
64 ms
64 ms
64 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
8
13/2/11
13/2/11
13/2/12
13/2/12
8
16
18
1 GB
Rev. 1.22, 2007-01
12
03292006-CXBY-V2JX
QIMONDA [ QIMONDA AG ]
