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HYI18T1G800C2C-3.7 参数 Datasheet PDF下载

HYI18T1G800C2C-3.7图片预览
型号: HYI18T1G800C2C-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 70 页 / 3976 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F](L)  
1-Gbit Double-Data-Rate-Two SDRAM  
7.4  
ODT AC Electrical Characteristics  
This chapter describes the ODT AC electrical characteristics.  
TABLE 44  
ODT AC Characteristics and Operating Conditions for DDR2–1066  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
1)  
tAOND  
tAON  
ODT turn-on delay  
2
2
nCK  
ns  
1)2)3)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 2.575  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2  
3 tCK .AVG+ tAC.MAX + 1  
ns  
4)5)  
2.5  
2.5  
nCK  
ns  
4)5)6)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
t
AC.MIN + 2  
2.5 tCK.AVG + tAC.MAX + 1  
ns  
ODT to Power Down Mode Entry Latency 4  
ODT Power Down Exit Latency 11  
nCK  
nCK  
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when  
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted as 2 clock cycles after the clock edge that registered a  
first ODT HIGH counting the actual input clock edges.  
2) Timings are specified with DQs and DM input slew rate of 1.0V/ns. See Specific Notes on derating for other slew rate values.  
3) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock (output  
deratings are relative to the SDRAM input clock).  
For example, if the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per).MIN = - 202 ps and tERR(6-10per).MAX = + 223 ps, then  
t
DQSCK.MIN(derated) = tDQSCK.MIN - tERR(6-10per).MAX = - 300 ps - 223 ps = - 523 ps and tDQSCK.MAX(derated) = tDQSCK.MAX - tERR(6-10per).MIN = 300 ps +  
202 ps = + 502 ps.  
Similarly, tLZ.DQ for DDR2-1066 derates to tLZ.DQ,min(derated) = - 700 ps - 223 ps = - 923 ps and  
t
LZ.DQ.MAX(derated) = 350 ps + 202 ps = + 552 ps. (Caution on the min/max usage!)  
4) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
Both are measured from tAOFD, which is interpreted as 0.5 x tCK.AVG [ns] after the second trailing clock edge counting from the clock edge  
that registered a first ODT LOW and by counting the actual input clock edges. For DDR2-1066, this is 0.9375 [ns] (= 0.5 x 1.875 [ns]) after  
the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.  
5) For tAOFD of DDR2-1066, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH.AVG, average input clock HIGH pulse width of 0.5 relative to  
t
CK.AVG. tAOF.MIN and tAOF.MAX should each be derated by the same amount as the actual amount of tCH.AVG offset present at the DRAM input  
with respect to 0.5. For example, if an input clock has a worst case tCH.AVG of 0.48, the tAOF.MAX should be derated by subtracting 0.02 x  
CK.AVG from it, whereas if an input clock has a worst case tCH.AVG of 0.52, the tAOF.MAX should be derated by adding 0.02 x tCK.AVG to it.  
Therefore, we have; tAOF.MIN(derated) = tAC.MIN - [0.5 - Min(0.5, tCH.AVG.MIN)] x tCK.AVG AOF.MAX(derated) = tAC.MAX + 0.6 + [Max(0.5, tCH.AVG.MAX) - 0.5]  
t
t
x tCK.AVGortAOF.MIN(derated) = Min(tAC.MIN, tAC.MIN - [0.5 - tCH.AVG.MIN] x tCK.AVG)tAOF.MAX(derated) = 0.6 + Max(tAC.MAX, tAC.MAX + [tCH.AVG.MAX - 0.5] x t  
CK.AVG) where tCH.AVG.MIN and tCH.AVG.MAX are the minimum and maximum of tCH.AVG actually measured atthe DRAM input balls. Note that  
these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations  
shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF aretAOF.MIN(derated_final)  
=
t
t
AOF.MIN(derated) + { - tJIT.DUT.MAX - tERR(6-10per).MAX  
AOF.MAX(derated_final) = tAOF.MAX(derated) + { - tJIT.DUTY.MIN - tERR(6-10per).MIN  
}
}
6) When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT.DUTY.MAX - tERR(6-10per).MAX } and { - tJIT.DUTY.MIN  
- tERR(6-10per).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per).MIN = - 202 ps, tERR(6-10per).MAX = + 223 ps, tJIT.DUTY.MIN = - 66  
ps and tJIT.DUTY.MAX = + 74 ps, then tAOF.MIN(derated) = tAOF.MIN + { - tJIT.DUTY.MAX - tERR(6-10per).MAX } = - 350 ps + { - 74 ps - 223 ps} = - 647 ps and  
t
AOF.MAX(derated) = tAOF.MAX + { - tJIT.DUTY.MIN - tERR(6-10per).MIN } = 950 ps + { 66 ps + 202 ps } = + 1218 ps. (Caution on the min/max usage!)  
Rev. 1.60, 2008-08  
56  
09262007-3YK7-BKKG  
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