Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 42
Absolute Jitter Value Definitions
Symbol Parameter
Min.
Max.
Unit
tCK.ABS
tCH.ABS
Clock period
t
t
CK.AVG(Min) + tJIT.PER(Min)
t
CK.AVG(Max) + tJIT.PER(Max)
CH.AVG(Max) x tCK.AVG(Max) +
ps
ps
Clock high-pulse width
CH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min)
t
tJIT.DUTY(Max)
tCL.ABS
Clock low-pulse width
tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max)
+
ps
tJIT.DUTY(Max)
Example: for DDR2-667, tCH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 43 shows clock-jitter specifications.
TABLE 43
Clock-Jitter Specifications for DDR2–667, DDR2–800 and DDR2–1066
DDR2–667 DDR2–800 DDR2–1066 Unit
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
tCK.AVG
tJIT.PER
Average clock period nominal w/o jitter
3000 8000 2500 8000 1875 7500 ps
–125 125 –100 100 –90 90 ps
–100 100 –80 80 –160 160 ps
–250 250 –200 200 –180 180 ps
Cycle-to-cycle clock-period jitter during DLL-locking period –200 200 –160 160 –160 160 ps
Clock-period jitter
tJIT(PER,LCK) Clock-period jitter during DLL locking period
tJIT.CC
Cycle-to-cycle clock-period jitter
tJIT(CC,LCK)
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
–175 175 –150 150 –132 132 ps
–225 225 –175 175 –157 157 ps
–250 250 –200 200 –175 175 ps
–250 250 –200 200 –188 188 ps
–350 350 –300 300 –250 250 ps
tERR(6-10PER) Cumulative error across n cycles with n = 6 .. 10, inclusive
tERR(11-50PER) Cumulative error across n cycles with n = 11 .. 50, inclusive –450 450 –450 450 –425 425 ps
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
0.48 0.52 0.48 0.52 0.48 0.52 tCK.AVG
0.48 0.52 0.48 0.52 0.48 0.52 tCK.AVG
–125 125 –100 100 –75 75
ps
Rev. 1.60, 2008-08
55
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
