Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
7.3
Jitter Definition and Clock Jitter Specification
Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. Input clock jitter
specification parameters are applicable to DDR2-667, DDR2-800 and DDR2-1066.
The following table provides an overview of the terminology.
TABLE 41
Average Clock and Jitter Symbols and Definition
Symbol
Parameter
Description
Units
tCK.AVG
Average clock period tCK.AVG is calculated as the average clock period within any consecutive ps
200-cycle window:
ꢈ
ꢇ
ꢃ
ꢉꢉꢉꢉ
ꢈ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ ꢂꢊ
ꢊ
ꢀ
ꢇ
N = 200
tJIT.PER
Clock-period jitter
t
t
JIT.PER is defined as the largest deviation of any single tCK from tCK.AVG
JIT.PER = Min/Max of {tCKi – tCK.AVG} where i = 1 to 200
:
ps
t
t
JIT.PER defines the single-period jitter when the DLL is already locked.
JIT.PER is not guaranteed through final production testing.
t
JIT(PER, LCK)
Clock-period jitter
during DLL-locking
period
t
JIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking ps
period only.
t
JIT(PER,LCK) is not guaranteed through final production testing.
tJIT.CC
Cycle-to-cycle clock
period jitter
t
JIT.CC is defined as the absolute difference in clock period between two ps
consecutive clock cycles:
t
JIT.CC = Max of ABS{tCKi+1 – tCKi}
t
t
JIT.CC defines the cycle - to - cycle jitter when the DLL is already locked.
JIT.CC is not guaranteed through final production testing.
t
JIT(CC, LCK)
Cycle-to-cycle clock
period jitter during
DLL-locking period
t
JIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking
ps
period only.
t
JIT(CC,LCK) is not guaranteed through final production testing.
tERR.2PER
Cumulative error
across 2 cycles
t
ERR.2PER is defined as the cumulative error across 2 consecutive cycles ps
from tCK.AVG
:
ꢇ
ꢀ
ꢎ
ꢂ
ꢈ
ꢋꢀꢁ ꢁ ꢂ ꢌꢃ ꢍ
ꢁ
ꢋꢄ ꢅꢆ
ꢂ
ꢎ
ꢋ ꢄꢅ ꢉꢏ ꢊ
ꢆ
ꢁ
ꢇ
n = 2 for tERR(2per)
where i = 1 to 200
Rev. 1.60, 2008-08
53
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
