欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYE18M1G16 参数 Datasheet PDF下载

HYE18M1G16图片预览
型号: HYE18M1G16
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位x16的移动DDR -RAM [1-Gbit x16 DDR Mobile-RAM]
分类和应用: 双倍数据速率
文件页数/大小: 65 页 / 3507 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYE18M1G16的Datasheet PDF文件第2页浏览型号HYE18M1G16的Datasheet PDF文件第3页浏览型号HYE18M1G16的Datasheet PDF文件第4页浏览型号HYE18M1G16的Datasheet PDF文件第5页浏览型号HYE18M1G16的Datasheet PDF文件第7页浏览型号HYE18M1G16的Datasheet PDF文件第8页浏览型号HYE18M1G16的Datasheet PDF文件第9页浏览型号HYE18M1G16的Datasheet PDF文件第10页  
Data Sheet  
HY[B/E]18M1G16[0/1]BF  
1-Gbit DDR Mobile-RAM  
1.3  
Description  
The HY[B/E]18M1G16[0/1]BF is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is  
internally configured as a quad-bank DRAM.  
The HY[B/E]18M1G16[0/1]BF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate  
architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at  
the I/O balls. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data  
transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O balls.  
The HY[B/E]18M1G16[0/1]BF is especially designed for mobile applications. It operates from a 1.8V power supply. Power  
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced  
by using the programmable Partial Array Self Refresh (PASR).  
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD)  
mode. For further power-savings the clock may be stopped during idle periods.  
The HY[B/E]18M1G16[0/1]BF is housed in a 60-ball PG-VFBGA-60-6 package. It is available in Commercial (-0°C to +70°C)  
and Extended (-25°C to +85°C) temperature range.  
This product provides two options in Clock Enable (CKE) configurations – 1 CKE and 2 CKE, in addition to the 2 Chip Select  
scheme. The options provide independent control of CS and CKE of each DRAM dies as required to achieve low power  
consumption.  
For example, a possible combination is that while one DRAM die is in active mode, the other could be in standby via  
independent CS control, or in Deep Power Down mode via independent CS and CKE control. As shown in Table 26 SDRAM  
Maximum Operating Currents, number of figures for various scenarios are demonstrated, where one die is in active mode  
controlled by CS0; the other is in standby mode controlled by CS1 (for 1 CKE option), or in Power-Down mode controlled by  
CKE1 (for 2 CKE option).  
The HY[B/E]18M1G16[0/1]BF package contains two dies, each die assigned a separate chip select, which is functionally  
equivalent to having two seperate BGA components, with each component containing one die. The same functional limitations  
apply and care must be taken to avoid possible bus contention, since both dies share the same data bus. Any back-to-back  
read or write from a different die can only start when the existing burst operation is completed. For example, restricted  
operations involving two dies may include:  
Consecutive READ/WRITE bursts,  
Random READ/WRITE accesses,  
READ or WRITE truncations, and  
Simultaneous READ or WRITE on both dies  
In case of an ongoing read burst, the Burst Terminate (BST) command can be used before any access from the different die  
occurs.  
The dual-die device must follow the predefined command sequences for power-up and initialization. The operation can be  
performed for the two dies together or separately.  
Note: All the timing diagrams of operations shown int the following sections assume that operations occur within the same die.  
Rev.1.0, 2007-03  
6
10242006-Y557-TZXW