Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
2.4.6
WRITE
WRITE bursts are initiated with a WRITE command, as
shown in Figure 23. Basic timings for the DQs are shown in
Figure 24; they apply to all write operations.
The starting column and bank addresses are provided with
the WRITE command, and Auto Precharge is either enabled
or disabled for that access. If Auto Precharge is enabled, the
row being accessed is precharged at the completion of the
write burst. For the generic WRITE commands used in the
following illustrations, Auto Precharge is disabled.
FIGURE 23
WRITE Command
#,+
#+%
#3
ꢃ(IGHꢄ
2!3
#!3
7%
!ꢀꢅ!ꢆ
#!
%NABLE !0
!0
!ꢂꢀ
$ISABLE !0
"!ꢀꢁ"!ꢂ
"!
ꢇ $ONgT #ARE
"! ꢇ "ANK !DDRESS
#! ꢇ #OLUMN !DDRESS
!0 ꢇ !UTO 0RECHARGE
FIGURE 24
Basic WRITE Timing Parameters for DQs
#,+
T)(
T)3
$1-
$1
T)(
T)3
$) N
$) Nꢁꢂ
ꢀ $ONgT #ARE
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and subsequent data
elements are registered on each successive positive edge of CLK. Upon completion of a burst, assuming no other commands
have been initiated, the DQs remain in High-Z state, and any additional input data is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Rev. 1.22, 2006-12
28
01132005-06IU-IGVM
QIMONDA [ QIMONDA AG ]
