Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
2.4.5.4
READ to WRITE
A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed to the same
or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is recommended that the DQs
are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either delaying the WRITE command, or
suppressing the data-out from the READ by pulling DQM HIGH two clock cycles prior to the WRITE command, as shown in
Figure 21. With the registration of the WRITE command, DQM acts as a write mask: when asserted HIGH, input data will be
masked and no write will be performed.
FIGURE 21
READ to WRITE Timing
#,+
2%!$
./0
./0
./0
./0
72)4%
./0
./0
#OMMAND
!DDRESS
$1-
"A !ꢀ
#OL N
"A !ꢀ
#OL B
#,ꢃꢈ
(IGHꢅ:
$/ N
$/ Nꢊꢆ
$) B
$) Bꢊꢆ
$) Bꢊꢈ
$1
$1
#,ꢃꢉ
(IGHꢅ:
$/ N
$) B
$) Bꢊꢆ
$) Bꢊꢈ
ꢃ $ONgT #ARE
"A !ꢀ #OL N ꢁBꢂ ꢃ BANK !ꢀ COLUMN N ꢁBꢂ
$/ N ꢃ $ATA /UT FROM COLUMN Nꢄ $) B ꢃ $ATA )N TO COLUMN Bꢄ
$1- IS ASSERTED ()'( TO SET $1S TO (IGHꢅ: STATE FOR ꢆ CLOCK CYCLE PRIOR TO THE 72)4% COMMANDꢇ
Rev. 1.22, 2006-12
01132005-06IU-IGVM
26
QIMONDA [ QIMONDA AG ]
