Data Sheet.
HY[B/E]18L512160BF-7.5
512-Mbit Mobile-RAM
TABLE 12
Timing Parameters for READ
Parameter
Symbol
- 7.5
Units
Notes
min.
max.
Access time from CLK
CL = 3
CL = 2
tAC
–
–
5.4
6.0
—
7.0
—
2
—
—
100k
—
ns
–
tAC
ns
ns
ns
ns
tCK
ns
ns
ns
ns
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
tLZ
tHZ
1.0
3.0
2.5
—
67
19
45
19
—
—
—
tOH
tDQZ
tRC
tRCD
tRAS
tRP
—
1)
1)
1)
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:no. of clock cycles = specified
delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS latency after
the READ command. Each subsequent data-out element is valid nominally at the next positive clock edge. Upon completion
of a READ burst, assuming no other READ command has been initiated, the DQs go to High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
FIGURE 13
Single READ Burst (CAS Latency = 2)
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Rev. 1.22, 2006-12
01132005-06IU-IGVM
21
QIMONDA [ QIMONDA AG ]
