Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
1.3
Description
The HY[B/E]18L256160B[C/F]L is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L256160B[C/F]L is especially designed for
mobile applications. It operates from a 1.8 V power supply.
Power consumption in self refresh mode is drastically
reduced by an On-Chip Temperature Sensor (OCTS); it can
further be reduced by using the programmable Partial Array
Self Refresh (PASR).
The HY[B/E]18L256160B[C/F]L achieves high speed data
transfer rates by employing
a chip architecture that
prefetches multiple bits and then synchronizes the output
data to the system clock. Read and write accesses are burst-
oriented; accesses start at a selected location and continue
for a programmed number of locations (1, 2, 4, 8 or full page)
in a programmed sequence.
A conventional data-retaining Power Down (PD) mode is
available as well as a non-data-retaining Deep Power Down
(DPD) mode.
The HY[B/E]18L256160B[C/F]L is housed in a 54-ball P-
VFBGA package. It is available in Commercial (0 °C to +70
°C) and Extended (-25 °C to +85 °C) temperature ranges.
The device operation is fully synchronous: all inputs are
registered at the positive edge of CLK.
FIGURE 2
Functional Block Diagram
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Rev. 1.73, 2006-09
5
01302004-CZ2R-J9SE
QIMONDA [ QIMONDA AG ]
