Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
4 banks × 4 Mbit × 16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
8192 refresh cycles / 64 ms
Auto precharge
Commercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range
54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
•
•
•
•
•
Low supply voltages: VDD = 1.65V to 1.95V, VDDQ = 1.65V to 1.95V
Optimized self refresh (IDD6) and standby currents (IDD2 / IDD3
)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
TABLE 1
Performance
Part Number Speed Code
- 7.5
Unit
Speed Grade
133
5.4
6.0
7.5
9.5
MHz
ns
Access Time (tACmax
)
CL = 3
CL = 2
CL = 3
CL = 2
ns
Clock Cycle Time (tCKmin
)
ns
ns
TABLE 2
Memory Addressing Scheme
Item
Addresses
Banks
BA0, BA1
A0 - A12
A0 - A8
Rows
Columns
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
3
QIMONDA [ QIMONDA AG ]
