Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
2.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational procedures other than
those specified may result in undefined operation.
FIGURE 3
Power-Up Sequence and Mode Register Sets
9ꢀ'ꢀ'ꢀ
9'ꢀ ꢀ'ꢀ4ꢀ
ꢂꢃꢀ ꢀꢃꢀꢀVꢀ
Wꢀ
Wꢀ
Wꢀ
W5ꢀ ꢀ)&ꢀ ꢀ
Wꢀ
Wꢀ
05ꢀ ꢀ'ꢀ
&ꢀ.ꢀ
5ꢀ3ꢀ
5ꢀ)&ꢀ ꢀ
0ꢀ5ꢀ'ꢀ
&ꢀ/ꢀ.ꢀ
&ꢀ.(ꢀ ꢀ
12ꢀ 3ꢀ ꢀ
3ꢀ5(ꢀ ꢀ
$ꢀ5)ꢀ ꢀ
$ꢀ5)ꢀ ꢀ
0ꢀ56ꢀ ꢀ
&2ꢀ 'ꢀ (ꢀ ꢀ
&2ꢀ 'ꢀ (ꢀ ꢀ
0ꢀ56ꢀ ꢀ
&2ꢀ 'ꢀ (ꢀ ꢀ
&2ꢀ 'ꢀ (ꢀ ꢀ
1$ꢀ2&7ꢀ3ꢀ
152ꢀ$ꢀ3ꢀꢀ ꢀ
152ꢀ$ꢀ3ꢀꢀ ꢀ
&ꢀRPꢀ ꢀPDꢀ ꢀQꢀGꢀ
$ꢀGꢀGꢀUHꢀ ꢀVꢀVꢀ
$ꢀꢁꢀꢃꢀ
$ꢀOꢀOꢀ
%ꢀDꢀQꢀNVꢀ ꢀ
1%2ꢀꢀ$3ꢀꢀ ꢀ
%$ꢀ ꢀꢃꢀꢒꢀ%$ꢀ ꢀꢁꢀ
%ꢀ$ꢀꢃ ꢀ ꢀ/ꢀ
%ꢀ$ꢀꢁ ꢀ ꢀ/ꢀ
%ꢀ$ꢀꢃ ꢀ ꢀ/ꢀ
%$ꢀ ꢀꢁꢀ ꢀ+ꢀ
'ꢀ40ꢀ ꢀ
'ꢀ4ꢀ
ꢐ+ꢀ ꢀꢀ/ꢀHꢀYHꢀ ꢀOꢀꢑꢀ
ꢐꢀ+ꢀLꢀJꢀKꢀꢌꢀ=ꢑꢀꢀ
3ꢀRꢀZꢀHUꢀꢀꢌꢀXSꢀ ꢀꢍꢀ
9'ꢀ ꢀ'ꢀꢀDQꢀ ꢀGꢀꢀ&ꢀ.ꢀꢀVWꢀDꢀ ꢀEꢀOꢀHꢀ
/ꢀRꢀDꢀGꢀ
/ꢀRꢀDꢀGꢀ
([ꢀ Wꢀꢀꢎꢀ
0Rꢀ ꢀGꢀHꢀ
5ꢀHꢀJLꢀꢀVWꢀHꢀ ꢀUꢀ
0Rꢀ ꢀGHꢀ ꢀ
5ꢀHꢀJLꢀꢀVWꢀHꢀ ꢀUꢀ
ꢀꢀ'ꢀRꢀQꢀꢏWꢀꢀꢀ&ꢀDꢀUꢀHꢀ
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ
are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each
followed by NOP or DESELECT commands for at least tMRD period; the order in which both registers are programmed is
not important. Programming of the Extended Mode Register may be omitted when default values (half drive strength, 4 bank
refresh) will be used.
Following these steps, the Mobile-RAM is ready for normal operation.
Rev. 1.73, 2006-09
8
01302004-CZ2R-J9SE
QIMONDA [ QIMONDA AG ]
