HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
#OMMAN
./0
72)4%
./0
./0
"34
./0
./0
"A !ꢏ
#OL N
!
RESS
$) N
$) Nꢔꢀ
$) Nꢔꢁ
$1
ꢒ $ONgT #ARE
"A !ꢏ #OL N ꢒ "ANK !ꢏ #OLUMN N
$) N ꢒ $ATA )N TO COLUMN N
"URST ,ENGTH ꢒ ꢈ IN THE CASE SHOWNꢐ
ꢁ SUBSEQUENT ELEMENTS OF $ATA )N ARE WRITTEN IN THE PROGRAMME OR ER FOLLOWING $) Nꢐ
4HE BURST IS TERMINATE AFTER THE ꢆR ATA ELEMENTꢐ
Figure 30 Terminating a WRITE Burst
2.4.6.2
Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 31.
#,+
#+%
INTERNAL
CLOCK
./0
72)4%
./0
./0
./0
#OMMAN
RESS
"A !ꢏ
#OL N
!
T#3,
T#3,
T#3,
$) N
$) Nꢔꢀ
$) Nꢔꢁ
$1
ꢒ $ONgT #ARE
"A !ꢏ #OL N ETCꢐ ꢒ "ANK !ꢏ #OLUMN N ETCꢐ
$/ N ETCꢐ ꢒ $ATA /UT FROM COLUMN N ETCꢐ
#, ꢒ ꢁ IN THE CASE SHOWN
#LOCK SUSPEN LATENCY T#3, IS ꢀ CLOCK CYCLE
Figure 31 Clock Suspend Mode for WRITE Bursts
Data Sheet
28
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
