HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsAC Characteristics
Table 20
Electrical Characteristics1)
Parameter
Symbol
Values
Unit Notes
min.
max.
Power Supply Voltage
VDD
VDDQ
VIH
VIL
1.70
1.70
1.95
1.95
DDQ + 0.3
V
—
Power Supply Voltage for DQ Output Buffer
Input high voltage
V
—
2)
0.8 × VDDQ
V
V
Input low voltage
-0.3
0.3
—
V
Output high voltage (IOH = -0.1 mA)
Output low voltage (IOL = 0.1 mA)
Input leakage current
VOH
VOL
IIL
V
DDQ - 0.2
V
—
—
—
—
–
0.2
1.0
1.5
V
-1.0
-1.5
µΑ
µA
Output leakage current
IOL
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); all voltages referenced to VSS. VSS and VSSQ must be at same
potential.
2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.
Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level.
3.2
AC Characteristics
Table 21
AC Characteristics1)2)3)4)
Parameter
Symbol
tCK
- 7.5
Unit Notes
min.
7.5
max.
Clock cycle time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
—
ns
—
9.5
—
—
ns
Clock frequency
fCK
133
105
5.4
6.0
—
MHz
MHz
ns
—
—
5)6)
Access time from CLK
tAC
—
—
ns
Clock high-level width
tCH
tCL
tIS
2.5
2.5
1.5
0.5
0.8
2
ns
—
Clock low-level width
—
ns
—
7)
Address, data and command input setup time
Address and command input hold time
Data (DQ) input hold time
—
ns
tIH
—
ns
—
ns
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
tMRD
tLZ
—
tCK
ns
—
—
—
1.0
3.0
2.5
—
—
tHZ
7.0
—
ns
tOH
ns
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
tDQZ
tDQW
tRC
2
tCK
tCK
ns
—
0
—
—
8)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
67
19
15
45
—
tRCD
tRRD
tRAS
—
ns
—
ns
100k
ns
Data Sheet
46
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
QIMONDA [ QIMONDA AG ]
