Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
3
Functional Description
This chapter list all defined commands and their usage for this Synchronous DRAM family.
TABLE 4
Truth Table: Operation Command
Operation
Device State
CKE
CKE
n1)2)
DQM BA0
AP=
Addr. CS RAS CAS WE
1)2)
1)2)
1)2)
1)2)
1)2)
1)2)
n-11)2)
BA11)2) A101)2)
Bank Active
Bank Precharge
Precharge All
Write
Idle3)
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
L
V
X
X
V
V
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
Any
L
Any
H
L
L
Active3)
Active3)
H
H
Write with Auto
precharge
H
L
Read
Active3)
Active3)
H
H
X
X
X
X
V
V
L
V
V
L
L
H
H
L
L
H
H
Read with Auto
precharge
H
Mode Register Set
No Operation
Idle
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
L
L
L
L
L
Any
H
H
X
L
H
H
X
L
H
L
Burst Stop
Active
L
Device Deselect
Auto Refresh
Any
H
L
X
H
H
X
X
X
X
Idle
Self Refresh Entry
Self Refresh Exit
Idle
L
L
L
Idle (Self Refr.)
H
H
L
X
H
X
X
X
H
X
X
Clock Suspend Entry Active
H
H
L
L
X
X
X
X
X
X
X
X
X
H
Power Down Entry
(Precharge or active
standby)
Idle
Active
Active4)
L
H
X
X
H
X
H
X
X
H
X
H
X
X
L
Clock Suspend Exit
Power Down Exit
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Any (Power
Down)
Data Write/Output
Enable
Active
H
H
X
X
L
X
X
X
X
X
X
X
X
Data Write/Output
Disable
Active
H
X
X
X
X
1) V = Valid, X = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend
mode.
Rev. 1.00, 2006-10
12
10302006-7FCJ-R0SX
QIMONDA [ QIMONDA AG ]
