Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 9
DC Characteristics
Parameter
Symbol
Values
Unit Note/
Test Condition
Min. Max.
1)2)
1)2)
1)2)3)
1)2)3)
1)2)
1)2)
1)
Supply Voltage
VDD
VDDQ
VIH
3.0 3.6
3.0 3.6
V
V
I/O Supply Voltage
Input high voltage
2.0
VDDQ+0.3 V
Input low voltage
VIL
– 0.3 +0.8
V
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
VOH
VOL
2.4
–
–
V
0.4
V
Input leakage current, any input(0 V < VIN < VDD, all other inputs = 0 V) IIL
– 5 +5
– 5 +5
μA
μA
1)
Output leakage current(DQs are disabled, 0 V < VOUT < VDDQ
)
IOL
1) TA = 0 to 70 ºC
2) All voltages are referenced to VSS
3)
V
IH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 10
Input and Output Capacitances
Parameter
Symbol
Values1)
Unit
Note
Min.
Max.
2)
2)
Input Capacitances: CK
CI1
CI2
2.5
2.5
3.5
3.8
pF
pF
Input Capacitance
(A0-A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
2)
Input/Output Capacitance (DQ)
CI0
4.0
6.0
pF
1) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
2) TA = 0 to 70 ºC; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz
Rev. 1.32, 2007-10
13
10122006-I6LJ-WV3H
QIMONDA [ QIMONDA AG ]
