Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
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$ꢉ
$ꢈ
$ꢇ
$ꢆ
&/
$ꢂ
$ꢅ
%7
$ꢄ
$ꢃ
%/
$ꢁ
:%/
70
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Z
Z
Z
Z
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03%6ꢁꢁꢁꢃ
TABLE 6
Mode Register Definition (BA1:0 = 00B)
Field
BL
Bits
Type
Description
2:0
w
Burst Length
Number of sequential bits per DQ related to one read/write command
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
1
2
4
8
111B Full Page (Sequential burst type only)
BT
CL
3
Burst Type
0B
1B
Sequential
Interleaved
6:4
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
TM
8:7
Test Mode
Note: All other bit combinations are RESERVED.
00B Mode register set
WBL
9
Write Burst Length
0B
1B
Burst write
Single bit write
12:10
Reserved, set to zero
Rev. 1.32, 2007-10
10
10122006-I6LJ-WV3H
QIMONDA [ QIMONDA AG ]
