Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition1)
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
2)3)4)5)
2)3)4)5)
Internal write to read command
delay
tWTR
2
—
1
—
tCK
ns
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
Exit self-refresh to read command tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual systemclock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
t
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
TABLE 21
AC Timing - Absolute Specifications for PC2700
Parameter
Symbol –7
Unit
Note/Test
Condition1)
DDR266A
Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
tAC
tCH
tCK
–0.75
+0.75
0.55
12
ns
tCK
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
0.45
Clock cycle time
7.5
CL = 3.0 3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
2)3)4)5)
7.5
12
7.5
12
CK low-level width
tCL
0.45
0.55
—
2)3)4)5)6)
2)3)4)5)
Auto precharge write recovery + precharge time tDAL
(tWR/tCK)+(tRP/tCK)
DQ and DM input hold time
tDH
0.5
—
2)3)4)5)6)
2)3)4)5)
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
tDIPW
tDQSCK
tDQSL,H
1.75
–0.75
0.35
—
+0.75
—
2)3)4)5)
Rev. 2.3, 2007-03
28
03062006-8CCM-VPUW
QIMONDA [ QIMONDA AG ]
